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data sheet 26301.104 a3938 three-phase power mosfet controller the a3938 is a three-phase, brushless dc motor controller. the a3938 high-current gate drive capability allows driving of a wide range of power mosfets and can support motor supply voltages to 50 v. the a3938 integrates a bootstrapped high-side driver to minimize the exter- nal component count required to drive n-channel mosfet drivers. internal xed off-time, pwm current-control circuitry can be used to regulate the maximum load current to a desired value. the peak load current limit is set by the user?s selection of an input reference volt- age and external sensing resistor. a user-selected external rc timing network sets the xed off-time pulse duration. for added exibility, the pwm input can provide speed/torque control where the internal current control circuit sets a limit on the maximum current. the a3938 includes a synchronous recti cation feature. this shorts out the current path through the power mosfet reverse body diodes dur- ing pwm off-cycle current decay. this can minimize power dissipation in the mosfets, eliminate the need for external power clamp diodes, and potentially allow a more economical choice for the mosfet drivers. the a3938 provides commutation logic for hall sensors con gured for 120-degree spacing. the hall input pins are pulled-up to an internally- generated 5 v reference. power mosfet protection features include: bootstrap capacitor charging current monitor, regulator undervoltage monitor, motor lead short-to-ground, and thermal shutdown. ? drives wide range of n-channel mosfets ? low-side synchronous recti cation ? power mosfet protection ? adjustable dead time for cross-con- duction protection ? selectable coast or dynamic brake on power-down or reset input ? fast/slow current decay modes use the following complete part numbers when ordering: ab so lute max i mum rat ings part number pins package a3938seq 32 plcc a3938slq 36 qsop A3938SLD 38 tssop load supply voltage, v bb ................................... 50 v vreg (transient) ............................................... 15 v logic input voltage range, v in ... ?0.3 v to v lcap +0.3 v sense voltage, v sense ........................... ?5 v to 1.5 v pins: sa, sb, sc................................... ?5 v to 50 v pins: gha, ghb, ghc .................. ?5 v to v bb + 17 v pins: ca, cb, cc ........................... sa/sb/sc + 17 v operating temperature range ambient temperature, t a ............. ?20c to +85c junction temperature, t j ............................ +150c storage temperature, t s .......... ?55c to +150c thermal impedance (typical), at t a = +25oc; measured on a jedec-standard "high-k" pcb a3938eq, r ja ........................................ 37c/w a3938ld, r ja ........................................ 38c/w a3938lq, r ja ........................................ 44c/w features ? internal pwm current control ? motor lead short-to-ground protection ? internal 5 v regulator ? fault diagnostic output ? thermal shutdown ? undervoltage protection a3938ld, 38-pin tssop a3938eq, 32-pin plcc a3938lq, 36-pin qsop
2 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 26301.104 a3938 three-phase power mosfet controller functional block diagram (this diagram shows only one of the three outputs) vreg regulator vbb charge pump dead-time adjust rc blanking fixed off-time vreg low-side driver high-side protection logic ca gha sa dead gla pgnd rc mode pwm sense to phase b ref c boot dir reset brake r t c t to phase c h2 h1 h3 low-side protection logic r s turn-on delay lcap 10 uf 0.1 uf 0.1 uf + 0.1 uf + fault agnd brksel brkcap power loss brake 4.7uf v reg uvlo vreg reset control logic o.d. invalid hall vreg undervoltage short to gnd tsd turn-on delay high-side driver + + a a for 12 v applications, vbb must be shorted to vreg. for this condition, the absolute maximum rating of 15 v on vreg must be maintained to prevent damage to the a3938.
3 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 26301.104 a3938 three-phase power mosfet controller electrical characteristics 1,2 unless otherwise noted: t a = 25c, v bb = 18 v to 50 v, c lcap = 0.1 f, c boot = 0.1 f, c vreg = 10 f, pwm = 22.5 khz, square wave, two phases active characteristics symbol test conditions min. typ. 1 max. units quiescent current i vbb reset = 1, coast mode, stopped ? ? 8.0 ma lcap regulator v lcap i lcap = ?3.0 ma 4.75 5 5.25 v vreg =vbb supply voltage range v reg vreg = vbb, observe maximum rating = 15 v 10.8 ? 13.2 v vreg output voltage v reg v bb = 13.2 v to 18 v, i vreg = ?10 ma ? v bb ? 2.5 ? v v bb = 18 v to 50 v, i vreg = ?10 ma 12.4 13 13.6 v vreg load regulation v regload i vreg = ?1 ma to ?30 ma, coast mode ? 25 ? mv vreg line regulation v reglin i vreg = ?10 ma, coast mode ? 40 ? mv control logic logic input voltage v in(1) minimum high level for logical 1 2.0 ? ? v v in(0) maximum low level for logical 0 ? ? 0.8 v logic input current i in(1) v in = 2.0 v ?30 ? ?90 a i in(0) v in = 0.8 v ?50 ? ?130 a gate drive low-side drive, output high v hgl i gx = 0 v reg ? 0.8 v reg ? 0.5 ? v high-side drive, output high v hgh i gx = 0 10.4 11.6 12.8 v pull-up switch resistance r ds(on) i gx = ?50 ma ? 14 ? ? pull-down switch resistance r ds(on) i gx = 50 ma ? 4 ? ? low-side switching, 10/90 rise time tr gl c load = 3300 pf ? 120 ? ns low-side switching, 10/90 fall time tf gl c load = 3300 pf ? 60 ? ns high-side switching, 10/90 rise time tr gh c load = 3300 pf ? 120 ? ns high-side switching, 10/90 fall time tf gh c load = 3300 pf ? 60 ? ns propagation delay; ghx,glx rising t pr pwm to gate drive out, c load = 3300 pf ? 220 ? ns propagation delay; ghx,glx falling t pf pwm to gate drive out, c load = 3300 pf ? 110 ? ns dead time, maximum t dead v dead = 0, ghx to glx, c load = 0 3.5 5.6 7.6 s dead time, minimum t dead i dead = 780 a, glx to ghx, c load = 0 50 100 150 ns continued on next page...
4 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 26301.104 a3938 three-phase power mosfet controller characteristics symbol test conditions min. typ. 1 max. units bootstrap capacitor bootstrap capacitor voltage v cx i cx = 0, v sx = 0, v reg = 13 v 10.4 11.6 12.8 v bootstrap r out r cx i cx = ?50 ma ? 9 12 ? charge current (source) i cx 100 ? ? ma current limit circuitry input offset voltage v io 0 v < v cmr < 1.5 v ? ? 5 mv input current , sense pin i b 0 v < v cm , v diff < 1.5 v ? ?25 ? a input current , reference pin i b 0 v < v cm , v diff < 1.5 v ? 0 ? a blank time t blank r = 56 k ? , c = 470 pf ? 0.91 ? s rc charge current i rc ?0.9 ?1 ?1.1 ma rc voltage threshold v rcl 1.0 1.1 1.2 v v rch 2.7 3.0 3.3 v protection circuitry bootstrap charge threshold i cx ghx turns on, and glx turns off, at i cx ? ?9 ? ma short to ground, drain-source monitor v dsh v bb ? v sx , high side on 1.3 2.0 2.7 v vreg undervoltage threshold uvlo v reg increasing 9.2 9.7 10.2 v v reg decreasing 8.6 9.1 9.6 v fault output voltage v out i ol = 1 ma ? ? 0.5 v brake capacitor supply current i brake v bb = 8 v, brksel = 1 ? 30 ? a low side gate voltage v glbh v bb =0, brkcap = 8v ? 6.6 ? v thermal shutdown temperature t j ? 165 ? c thermal shutdown hysteresis ? t j ?10? c electrical characteristics 1,2 (continued) unless otherwise noted: t a = 25c, v bb = 18 v to 50 v, c lcap = 0.1 f, c boot = 0.1 f, c vreg = 10 f, pwm = 22.5 khz, square wave, two phases active 1 typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. performance may vary for individual units, within the speci ed maximum and minimum limits. 2 negative current is de ned as conventional current coming out of (sourced from) the speci ed device terminal.
5 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 26301.104 a3938 three-phase power mosfet controller reset. a logic input that enables the device. has internal 50 k ? pull-up to lcap. setting reset to 1 coasts or brakes the motor, depending on the state of the brksel pin. set- ting reset to 0 enables the gate drive to follow commuta- tion logic. setting reset to 1 overrides the brake pin. gla/glb/glc. low-side gate drive outputs for external mosfet drivers. external series gate resistors can be used to control slew rate seen at the power driver gate, thereby controlling the di / dt and dv / dt of sx outputs. sa/sb/sc. directly connected to the motor terminals, these pins sense the voltages switched across the load. the pins are also connected to the negative side of the bootstrap capacitors and the negative supply connections for the oat- ing high-side drivers. gha/ghb/ghc. high-side gate drive outputs for n-channel mosfet drivers. external series gate resistors can be used to control slew rate seen at the power driver gate, thereby controlling the di / dt and dv / dt of sx outputs. ca/cb/cc. high-side connections for bootstrap capaci- tors, providing positive supply for high-side gate drivers. the bootstrap capacitors are charged to approximately vreg when the output sx terminals go low. when the outputs swing high, the voltages on these pins rise with the outputs to provide the boosted gate voltages needed for the n-channel power mosfets. mode. logic input to set current-decay mode. in response to a pwm off command, slow decay mode (mode = 1) switches off the high-side fet, and fast decay mode (mode = 0) switches off the high-side and low-side fets. has an internal 50 k ? pull-up to lcap. h1/h2/h3. hall sensor inputs with internal, 50 k ? pull-ups to lcap. con gured for 120-degree electrical spacing. dir. logic input to reverse rotation (see the table commu- tation truth table, on the next page). has internal, 50 k ? pull-up to lcap. fault. open-drain output to indicate fault condition. will be pulled high (usually by 5.1 k ? external pull-up) for any of the following fault conditions: ? invalid hall sensor input code (coasts the motor). ? undervoltage condition detected at vreg (coasts or brakes the motor depending on stored setting for brksel). ? thermal shutdown (coasts the motor). ? motor lead (sa/sb/sc) connected to ground (turns off only the high-side power mosfets). only the ?short-to-ground? fault is latched, but it is cleared at each commutation. if the motor has stalled due to a short- to-ground being detected, toggling the reset pin or repeat- ing a power-up sequence clears the fault. brake. logic input for braking function. setting brake to 1 turns on low-side mosfets, and turns off the high-side mosfets. this effectively shorts the bemf in the windings and brakes the motor. internal 50 k ? pull-up to lcap. set- ting reset to 1 overrides this brake pin. see also brksel. brkcap. this pin is for connection of the reservoir capacitor used to provide the positive power supply for the sink drive outputs for a power-down condition. this allows predictable braking, if desired. using a 4.7 f capacitor will provide 6.5 v gate drive for 300 ms. if the power-down brak- ing option is not needed (i.e., brksel = 0), then this pin should be tied to vreg. brksel . logic input to enable/disable braking upon power-down condition or reset = 1. internal 50 k ? pull-up to lcap. setting brksel to 0 enables coast mode. setting brksel to 1 enables brake mode. pwm. speed control input. setting pwm to 1 turns on mosfets selected by hall input logic. setting pwm to 0 turns off the selected mosfets. keep the pwm input held high to utilize internal current control circuitry. internal 50 k ? pull-up to lcap. rc. analog input. connection for r t and c t to set the xed off-time. c t also sets the blank time (see the section application information). it is recommended that the xed off-time should not be less than 10 s. the resistor should be in the range between 10 k ? and 500 k ? . vreg. regulated 13 v supply for the low-side gate drive and the bootstrap capacitor charge circuit. as a regulator, use a 10 f decoupling/storage capacitor (esr < 1 ? ) from this pin to agnd, as close to the device pins as possible. note: for 12 v applications, the vreg pin should be shorted to vbb. pin descriptions
6 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 26301.104 a3938 three-phase power mosfet controller vbb. motor power supply connection for the a3938 and for power mosfets. it is good practice to connect a decou- pling capacitor from this pin to agnd, as close to the device pins as possible. ref . analog input to current limit comparator. voltage applied here sets the peak load current according to the fol- lowing equation: i trip = v ref / r sense lcap . 5 v reference to power internal logic and provide low current for dead pin and fault pin. connection for 0.1 f external capacitor for decoupling. dead. analog input. a resistor between dead and lcap is selected to adjust turn-off time to turn-on time. this delay is needed to prevent cross-conduction in the external power mosfets. see the section application information for details on setting dead time. sense. analog input to the current limit comparator. voltage representing load current appears on this pin. voltage transients that are seen at this pin when the drivers turn on are ignored for period of time, t blank . agnd. analog reference ground. pgnd. return for low-side gate drivers. this should be connected to the pcb power ground. h1 h2 h3 dir gla glb glc gha ghb ghc sa sb sc 1011001100hi zlo 1001001010 z hilo 1101100010lohiz 0101100001lozhi 0111010001 zlohi 0011010100hiloz 1010100001lozhi 1000010001 zlohi 1100010100hiloz 0100001100hi zlo 0110001010 z hilo 0010100010lohiz commutation truth table mode pwm reset quadrant mode of operation** 0* 0 0 fast decay pwm chop ? current decay with opposite of selected low- side drivers on. 0* 1 0 fast decay selected drivers on. if current limiting, opposite of selected low-side drivers on. 1 0 0 slow decay pwm chop ? current decay with both low-side drivers on. 1 1 0 slow decay selected drivers on. if current limiting, both low-side drivers on. xx 1 x all high-side drivers off, low-sides see brksel stored. clears storable faults. * low-side, only, synchronous recti cation mode. **see commutation truth table for meaning of ?both? and "selected." input logic
7 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 26301.104 a3938 three-phase power mosfet controller synchronous recti cation. to reduce power con- sumption in the external mosfets, during the load current recirculation pwm-off cycle, the a3938 control logic turns on the appropriate low-side driver only . the reverse body diode of the power mosfet conducts only during the dead time required at each pwm transition, as usual. however, unlike full synchronous recti cation, the opposite high-side fet?s body diode (not the rdson) will carry the re-circulat- ing current, be self-extinguishing, and not force the motor to reverse direction. dead time. to prevent cross-conduction, it is required to have a delay between a high-side or low-side turn-off, and the next turn-on event. the potential for cross-conduction occurs with synchronous recti cation, direction changes, pwm, or after a bootstrap capacitor charging cycle. this dead-time is set via a resistor from the dead pin to lcap and can be varied from 100 ns to 5.5 s. for a nominal case, given: ? 25c ambient temperature, and ? 5.6 k ? < r dead < 470 k ? , t dead (nom,ns) = 37 + [(11.9 10 -3 ) (r dead + 500)] for predicting worst-case overvoltage and temperature extremes, use the following equations: t dead (min,ns) = 10 + [(6.55 10 -3 ) (r dead + 350)] t dead (max,ns) = 63 + [(17.2 10 -3 ) (r dead + 650)] for nominal comparison with i dead currents, also at 25c ambient temperature: i dead = (v lcap ? v be ) / (r dead + r int ) where v lcap = 5 v, v be = 0.7 v, and r int = 500 ? . rather than use r dead values near 470 k ? , set v dead = 0 v, which activates an internal (i dead = 10 a) current source. the choice of power mosfet and external gate resistance determines the selection of the dead-time resistor. the dead time should be made long enough to cover the variation of the mosfet capacitance and gate resistor tolerances (both external and internal to the a3938). decoupling. the internal reference vreg supplies current for the gate drive circuit. as the gates are driven high, they will require current from an external decoupling capacitor to support the transients. this capacitor should be placed as close as possible to the vreg pin. the value of the capacitor should be at least 20 times larger than the bootstrap capacitor. additionally, a 1 nf (or larger) ceramic monolithic capacitor should be connected between lcap and agnd, as close to the device pins as possible. protection circuitry. the a3938 has several protection features: ? bootstrap monitor . the bootstrap capacitor is charged whenever a sink-side mosfet is on, an sx output goes low, or load current recirculates. this happens constantly during normal operation. note: the high side will not be allowed to turn on before the charging has decayed to less than approximately 9 ma. ? undervoltage . vreg supplies the low-side gate driver and the bootstrap charge current. it is critical to ensure that the voltages are at a proper level before enabling any of the outputs. the undervoltage circuit is active during power-up and signals a fault, and also coasts or brakes (depending on the stored brksel setting) the motor during that time period, until vreg is greater than approximately 10 v. on powering down, a fault is signaled and the motor is coasted or braked, depending on the stored setting for brksel. ? hall invalid . illegal codes for the hall sensor inputs (0,0,0 or 1,1,1) force a fault and coast the motor. noisy hall lines may cause hall code errors, and therefore faults. additional external pull-up loading and ltering may be required in some systems. hint: use dividers to the vreg terminal, than to the lcap terminal, because the vreg terminal has more current capability. ? thermal shutdown . junction temperatures greater than 165 c cause the a3938 to signal a fault and coast the motor. ? motor lead . the a3938 signals a fault if the motor lead is shorted to ground. a short-to-ground is assumed after a high- side is turned on and greater than 2 v is measured between the drain (vbb) and source (sx) of the high-side power mosfet. this fault is cleared at the beginning of application information
8 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 26301.104 a3938 three-phase power mosfet controller each commutation. if a stalled motor results from a fault, the fault can only be cleared by toggling the reset pin or by a power-up sequence. current regulation. load current can be regulated by an internal xed off-time, pwm-control circuit. when the outputs of the mosfets are turned on, current increases in the motor winding until it reaches a value given by: i trip = v ref / r sense at the trip point, the sense comparator resets the source enable latch, turning off the source driver. at this point, load inductance causes the current to recirculate for the xed off- time period. the current path during recirculation is deter- mined by the con guration of the mode and sr input pins. the xed off-time is determined by an external resistor, r t , and capacitor, c t , connected in parallel from the rc terminal to agnd. the xed off-time is approximated by: t off = r t c t t off should be in the range between 10 s and 50 s. larger values for t off could result in audible noise problems. for proper circuit operation, 10 k ? < r t < 500 k ? . torque control can be implemented by varying the ref input voltage as long as the pwm input stays high. if direct control of the torque/current is desired by pwm input, a voltage can be applied to the ref pin to set an absolute maximum cur- rent limit. pwm blank. the capacitor c t also serves as the means to set the blank time duration. at the end of a pwm off-cycle, a high-side gate selected by the commutation logic turns on. at this time, large current transients can occur dur- ing the reverse recovery time, t rr , of the intrinsic body diodes of the power mosfets. to prevent false tripping of the sense comparator, the blank function disables the com- parator for a time period de ned by: t blank = 1.9 c t / (1 10 -3 ? [2 / r t ]) the user must ensure that c t is large enough to cover the current spike duration. braking. the a3938 dynamically brakes the motor by forcing all low-side power mosfets on, and all high-side power mosfets off. this effectively short-circuits the bemf and brakes the motor. during braking, the load cur- rent can be approximated by: i brakepeak = v bemf / r load as the current does not ow through the sense resistor dur- ing a dynamic brake, care should be taken to ensure that the maximum ratings of the power mosfets are not exceeded. note: on its rising edge, a reset setting of 1 overrides the brake input pin and latches the condition selected by the brksel pin. power loss brake. the brkcap and brksel pins provide a power-down braking option. a power-loss brake trigger event, which is either an undervoltage on vreg or a reset = 1 rising edge, is sensed by the a3938, which then dynamically brakes or coasts (depending on the stored brksel setting) the motor. the reservoir capacitor on the brkcap pin provides the positive voltage that forces the low-side gates of the power mosfets high, keeping them on, even after supply voltage is lost. a stored setting of brk- sel = 1 brakes the motor, but a stored setting of brksel = 0 coasts it. the combined effect of these settings is shown in the table brake control. brake brksel before power loss brake trigger event after power loss brake trigger event 0 0 normal run mode coast mode ? all gate drive outputs off 0 1 normal run mode brake mode ? all low-side gate drivers on 1 0 brake mode ? all low-side gate drivers on coast mode ? all gate drive outputs off 1 1 brake mode ? all low-side gate drivers on brake mode ? all low-side gate drivers on brake control
9 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 26301.104 a3938 three-phase power mosfet controller terminal list name description 32-lead a3938eq plcc 36-lead a3938lq qsop 38-lead a3938ld tssop pgnd low-side gate drive return 1 36 36 reset control input 2 1 1 glc low-side gate drive output, phase c 3 2 2 sc motor connection, phase c 4 3 3 ghc high-side gate drive output, phase c 5 6 6 cc bootstrap capacitor, phase c 6 7 7 glb low-side gate drive output, phase b 7 8 8 sb motor connection, phase b 8 9 9 ghb high-side gate drive output, phase b 9 10 10 cb bootstrap capacitor, phase b 10 11 11 gla low-side gate drive output, phase a 11 12 12 sa motor connection, phase a 12 13 13 gha high-side gate drive output, phase a 13 14 14 ca bootstrap capacitor, phase a 14 15 15 vreg gate drive supply 15 16 16 lcap 5 v output 16 17 17 fault diagnostic output 17 19 19 mode control input 18 20 20 vbb load supply 19 21 21 h1 hall control input 20 22 22 h3 hall control input 21 24 24 h2 hall control input 22 25 25 dir control input 23 26 26 brake control input 24 27 27 brkcap power loss brake reservoir capacitor 25 28 28 brksel control input 26 29 29 pwm control input 27 30 30 rc connection for fixed off-time r and c 28 31 31 sense sense resistor 29 32 32 ref current limit adjust 30 33 33 dead dead time adjust 31 34 34 agnd ground 32 35 35 n/c not connected 4,5,18,23 4, 5, 18, 23, 37, 38
10 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 26301.104 a3938 three-phase power mosfet controller a3938eq, 32-pin plcc fault 7 8 9 10 11 12 13 6 5 27 26 25 24 23 22 21 28 29 16 17 18 19 20 15 14 2 1 32 31 30 3 4 sense rc pwm brksel brkcap brake dir h2 h3 ghc cc glb sb ghb cb gla sa gha ca vreg lcap fault mode vbb h1 sc glc reset pgnd agnd dead ref control logic a3938lq, 36-pin qsop fault 7 8 9 10 11 12 13 6 5 30 29 28 27 26 25 24 31 32 15 16 17 18 14 1 2 3 4 22 21 20 19 23 36 35 34 33 sense rc pwm brksel brkcap brake dir h2 h3 n/c ghc cc glb sb ghb cb gla sa gha ca vreg lcap n/c reset glc sc n/c pgnd agnd dead ref n/c h1 vbb mode fault control logic .013 .008 0.32 0.19 .095 .060 2.41 1.52 .021 .013 0.53 0.33 .015 min 0.38 1.40 1.25 3.56 3.18 .453 .447 11.51 11.35 .495 .485 12.57 12.32 .553 .547 14.05 13.89 .595 .585 15.11 14.86 132 .050 bsc 1.27 base plane seating plane dimensions in inches metric dimensions (mm) in brackets, for reference only if unit is intended to be socketed, it is advisable to review lead profile with socket supplier .606 .598 15.40 15.20 .299 .291 7.60 7.40 .414 .398 10.51 10.11 .020 .011 0.51 0.28 0.85 bsc .033 0.80 ref .031 .012 .004 0.30 0.10 .104 .096 2.64 2.44 .050 .016 1.27 0.40 .013 .009 0.32 0.23 8? 0? .355 bsc 0.014 2 1 36 dimensions in millimeters u.s. customary dimensions (in.) in brackets, for reference only gauge plane seating plane
11 worcester, massachusetts 01615-0036 (508) 853-5000 115 northeast cutoff, box 15036 www.allegromicro.com data sheet 26301.104 a3938 three-phase power mosfet controller a3938ld, 38-pin tssop fault 7 8 9 10 11 12 13 6 5 30 29 28 27 26 25 24 31 32 15 16 17 18 14 1 2 3 4 22 21 20 19 23 36 35 38 37 34 33 sense rc pwm brksel brkcap brake dir h2 h3 n/c ghc cc glb sb ghb cb gla sa gha ca vreg lcap n/c n/c reset glc sc n/c pgnd agnd dead ref n/c h1 vbb mode n/c n/c control logic 0.20 0.09 0.008 0.004 8? 0? 0.75 0.45 0.030 0.018 1.10 max 0.043 0.15 0.05 0.006 0.002 0.27 0.17 0.011 0.007 4.5 4.3 0.177 0.169 6.4 bsc 0.252 1 ref 0.039 .50 bsc .020 .25 bsc 0.010 9.8 9.6 0.386 0.378 2 1 38 dimensions in millimeters u.s. customary dimensions (in.) in brackets, for reference only gauge plane seating plane the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical compo- nents in life-support devices or sys tems without express written approval. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon - si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. copyright?2003 allegromicrosystems, inc.

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